Table 11 Standard deviation of the simulation and proposed model
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
Workload | CMP | Cores | Cache hierarchy | NoC |
|---|---|---|---|---|
Multi-threaded (16 cores) | Baseline | 0.0153 | 0.0472 | 0.0144 |
Hybrid | 0.0198 | 0.0345 | 0.0169 | |
Multi-threaded (64 cores) | Baseline | 0.0653 | 0.0471 | 0.0336 |
Hybrid | 0.0393 | 0.0311 | 0.0435 | |
Multi-program (16 cores) | Baseline | 0.0123 | 0.0159 | 0.0692 |
Hybrid | 0.0258 | 0.0364 | 0.0696 | |
Multi-program (64 cores) | Baseline | 0.0123 | 0.0108 | 0.0250 |
Hybrid | 0.0258 | 0.0272 | 0.0435 |