Table 2 MB+FPU and OP implementations: synthesis results on FPGA
From: Dedicated object processor for mobile augmented reality - sailor assistance case study
Slices/Bram/F | Virtex 5 | Virtex 6 | Spartan 6 | Zynq (Artix) |
|---|---|---|---|---|
Nb/Nb/MHz | ||||
MB+FPU | 3,305 / 20 / 120 | 2,741 / 40 / 150 | 1,842 / 8 / 100 | - / - / 866 |
HW IP OP | 1,231 / 2 / 120 | 1,048 / 2 / 120 | 1,233 / 2 / 73 | 4,016 (LUTs) / 2 / 88 |