MixedSignal Architectures for HighEfficiency and LowDistortion Digital Audio Processing and Power Amplification
 Sergio Saponara^{1}Email author and
 Pierangelo Terreni^{1}
DOI: 10.1155/2010/394070
© S. Saponara and P. Terreni. 2010
Received: 9 June 2009
Accepted: 4 August 2009
Published: 8 November 2009
Abstract
The paper addresses the algorithmic and architectural design of digital input power audio amplifiers. A modelling platform, based on a meetinthemiddle approach between topdown and bottomup design strategies, allows a fast but still accurate exploration of the mixedsignal design space. Different amplifier architectures are configured and compared to find optimal tradeoffs among different costfunctions: low distortion, high efficiency, low circuit complexity and low sensitivity to parameter changes. A novel amplifier architecture is derived; its prototype implements digital processing IP macrocells (oversampler, interpolating filter, PWM crosspoint deriver, noise shaper, multilevel PWM modulator, dead time compensator) on a single lowcomplexity FPGA while offchip components are used only for the power output stage (LC filter and power MOS bridge); no heatsink is required. The resulting digital input amplifier features a power efficiency higher than 90% and a total harmonic distortion down to 0.13% at power levels of tens of Watts. Discussions towards the fullsilicon integration of the mixedsignal amplifier in embedded devices, using BCD technology and targeting power levels of few Watts, are also reported.
1. Introduction
Small size, lowcost and highefficiency audio amplifiers, integrated as much as possible with digital audio signal processing tasks in the same embedded device, are required in several consumer applications: home and car entertainment, computer/portable multimedia players and, for low power levels, hearing aids devices. Conventional linear amplifiers feature lowdistortion performance but have several disadvantages versus market needs [1, 2]: they are too heavy and energy inefficient and the achievable power density is limited by the physical size and cost of cooling hardware and power devices. An extra DigitaltoAnalog Converter (DAC) is needed, before the analog amplifier, for digital sources: CD, Super Audio CD and DVD supports, MP3 files, and Digital Audio Broadcasting.
1.1. The State of the Art of Digital Power Audio Amplifiers
A direct conversion of the input PCM stream to PWM is not useful: PWM is a nonlinear technique and the intermodulation between the PWM carrier frequency and the baseband audio signal leads to poorquality amplifiers [7]. To this aim, in academia and industry [8–24], several techniques have been proposed to improve the basic scheme in Figure 1: new digital audio processing algorithms [12–15, 17–20, 22–24] or novel feedback schemes [9–11, 21] or multilevel PWM power bridges [16] have been published to correct the distortions introduced by the PWM modulation or by the nonideal behaviour of the power stage. However the new proposed techniques require extra hardware resources; the performance gain is paid in terms of increased circuital complexity and cost. The overall amplifier often requires multiple chips for the digital part (including digital signal processor and/or ASIC and/or FPGA), plus ADC and highorder analog filters for the feedback plus multiple power transistors and gate drivers for multi level PWM. As a result highperformance systems require high circuit complexity, implemented using multiple chips and often multipleboards, and are not suitable for consumer applications or embedded devices. Solutions with lower complexity are usually obtained at the expense of audio quality reduction.
1.2. Aim and Outline of This Work
This work explores the design space of digital audio amplifiers to find an optimal mixing of different analog and digital techniques. The resulting architecture aims at achieving optimal performance in terms of lowdistortion and high power efficiency while still allowing a lowcost implementation: all the digital processing part integrated in a single device, for example, a lowcomplexity FPGA, plus offchip components only for the power stage, made up of a MOS Hbridge and an LC filter but without any heat sink.
Most stateoftheart techniques propose specific optimizations for just a part of the scheme in Figure 1; when integrating together different known techniques the relevant hardware overheads add up while the extra gain in performance can be negligible. However, the exhaustive design space exploration of digital power audio amplifiers is not straightforward since it needs fast but still accurate models involving the codesign of heterogeneous components: computation intensive processing algorithms at functional level with hardware components at physical level; low power digital and mixedsignal circuits with analog power devices; silicon integrated circuits with discrete devices. Hereafter Section 2 presents a platformbased modelling flow and the cost metrics used to drive the design space analysis. The models used to find optimal tradeoffs between complexity, power efficiency, distortion and sensitivity are presented in Section 3 together with architectural comparison results. Section 4 shows the prototyping of the selected architecture targeting power levels of tens of Watts. Section 5 compares the obtained results versus the state of the art and discusses the extension of the work to fully integrated amplifiers for power levels of few Watts. Conclusions are drawn in Section 6.
2. PlatformBased Design Flow and Metrics
2.1. Design Metrics Definition
The definition of the multiple cost metrics to be optimized is essential to drive the design space exploration and the correct comparison of different architectures. The design metrics are the audio signal distortion, the power efficiency, the circuit complexity and the architecture sensitivity to parameter changes. The input signals are PCM samples with a bit size n from 16 to 24 and a sample frequency between 44 kS/s and 96 kS/s (the lower values for frequency and bitsize are typical of audio CD while the higher values are used in audio DVD). The target output power, Pout, amounts to tens of Watts with power efficiency levels up to 90%. Reported data in this paper refer to the example case of max Pout of 70 Wrms (or 35 Wrms) delivered to a 4 (or 8 ) speaker. The total harmonic distortion (THD) considered for HighFidelity (HiFi) is a level lower than 0.2%, the optimal target is 0.1%. As discussed in [1] there are highend products for professional applications, using linear amplifiers, with THD figures below 0.001%; however the subjective sensitivity of the hearing human system to THD levels below 0.3% is often negligible. Most HiFi amplifiers, for example, Sony STRDE445 [13], for consumer home or car markets have a THD of 0.2%. The considered frequency response in this paper is 20 Hz–20 kHz, although THD optimizations focus on the range 500 Hz to 2 kHz where the hearing human system is mainly sensible and very often music signals are below 1617 kHz [1]. The target circuit complexity for the digital processing circuitry amounts to tens of equivalent ASIC gates, a value that can be fitted in a single lowcost FPGA leaving space to integrate other audio processing tasks thus realizing a complete audio acquisition/playing system in a single embedded device.
2.2. PlatformBased Design Flow
To allow a fast but still accurate design space exploration we followed a meetinthemiddle approach between bottomup and topdown strategies [25]. A configurable modelling platform has been built starting from libraries of analog and digital building block components. A library of accurate spice models has been derived bottomup for the hardware components whose nonideal characteristics and nonlinearity affect the behaviour of the power audio amplifier: power MOS, power supply, analog filters, OpAmp and comparators optionally used in the feedback loop. As example, we have created Spice models for the power MOS in [26], used also in the prototyping phase; such models consider all key electrical parameters [27] and their dependence on input driving signal ( ) and output delivered power: MOS transfer curves, drain source breakdown voltage , on resistance, gate charge , body diode reverse recovery charge , internal gate resistance , MOS rise and fall times and and switching frequency , transistor packaging and thermal characteristics. The Spice models have been integrated with parametric and fixedpoint Simulink models for the signal processing algorithms proposed to enhance the basic scheme in Figure 1, see details in Section 3. The resulting Spice/Simulink environment is then used topdown to build multiple architectures (proper configuring and combining the building block models) and to allow their fast but still accurate comparison. The considered design metrics are those in Section 2.1. This analysis allows a first selection of the most promising architectures; for them the comparison is further refined in a second step using HDL models for the digital audio algorithms.
Synthesized on different technologies (standardcells CMOS libraries or SRAMbased FPGAs) the HDL models permit the evaluation of the gate complexity and power consumption of the digital circuitry. The selected architectures are finally prototyped, and the real performances measured, using FPGA technology plus a discrete power output stage.
3. MixedSignal Architectural Exploration
3.1. Oversampler
To reduce the output THD an oversampler is added before the PCM to PWM conversion in the digital domain, see Figure 2. Oversampling by a parametric factor M is realized first inserting M1 zeros after each original sample (zero padding); the data stream is then processed with an interpolating filter to remove high frequency spurious repetitions of the baseband signal. The higher the oversampling factor M is, the higher ( ) the PWM carrier frequency is and hence the transition bandwidth for the LC output filter used to remove intermodulation distortion. Thus, a high oversampling factor M simplifies the design of the LC analog filter at the expense of an increased complexity for the digital interpolating filter.
Interpolating filter mask specifications.
Mas type  Passband  Stopband  Passband ripple  Stopband attenuation 

1  0.45  0.55  0.1 dB  50 dB 
2  0.4  0.6  0.02 dB  60 dB 
Once specified the magnitude response of the filter it is important to define its architectural implementation (FIR or IIR, windowing type, direct or cascade multistage structure, parallel or iterative implementation of the multiply and accumulateMAC unit, data bit width), since its hardware cost can represent the main bottleneck of the whole audio system [28–32].
FIR and IIR order for the interpolating filter, oversampling x8.
FIR  IIR  

Equiripple  Kaiser  Butt.  Cheb.  Elliptic  
Mask 1  193  233  38  13  7 
Mask 2  129  146  24  11  7 
Interpolating filter complexity and PWM frequency versus M.
M  Mas type  Equiripple  Kaiser 
 

order 
 order 
 kHz  
8  1  193  68.1  233  82.2  352.8 
8  2  129  45.5  146  51.5  
16  1  386  272.4  469  330.9  705.6 
16  2  257  181.3  291  205.3  
32  1  772  1089  938  1324  1411.2 
32  2  515  726,8  581  819,9  
64  1  1544  4358  1875  5292  2822.4 
64  2  1029  2904  1161  3277  
128  1  3087  17425  3749  21162  5644.8 
128  2  2057  11611  2321  13102 
From Table 3 it is clear that (i) the computational cost of a direct FIR implementation amounts to tens of millions MAC/s for and becomes prohibitive, in the range of tens of Giga MAC/s, when M grows up to 128; (ii) considering offchip power output bridges (see Section 3.6) with typical PWM frequencies within 1 MHz, oversampling factors M higher than 8 or 16 should be avoided.
 (1)
Polyphase filter implementation: in the oversampling unit 1 samples out of M are zeros (due to zero padding) and hence a polyphase structure reduces the required MAC operations for the interpolating filter by a factor M.
 (2)
Multistage cascade realization: the oversampling unit can be realized through a cascade of S multiple stages where the i th stage realizes an oversampling by a factor Mi (with ) with a filter of reduced order .
Interpolating filter complexity, polyphase, and multistage units.
Mask type  Filter type  Polyphase cost  Filter order, i th stage  




 
 
1  Equiripple  3.26  48  7  3  — 
2  Equiripple  3.26  32  11  5  — 
1  Kaiser  5.07  59  12  8  — 
2  Kaiser  4.72  37  15  10  — 
 
1  Equiripple  4.32  48  7  3  3 
2  Equiripple  4.32  32  11  5  3 
1  Kaiser  7.54  59  12  8  7 
2  Kaiser  7.89  37  15  10  9 
 
1  Equiripple  4.67  48  7  11  — 
2  Equiripple  5.20  32  11  16  — 
1  Kaiser  6.48  59  12  16  — 
2  Kaiser  6.48  37  15  20  — 
Comparing the results of Tables 3 and 4 it is clear that, exploiting the multistage decomposition and the polyphase techniques, the filter complexity is reduced to few millions of MAC/s.
The computational burden in Table 4 is roughly the same for the two mask types; in the rest of the work mask 2 is used since it ensures a lower passband ripple. Using the Equiripple filter type a computational saving of roughly 30% is achieved versus the Kaiser type.
By adopting an oversampling factor , 4stage polyphase FIR filter of Equiripple type with filter mask 2, the required complexity can be sustained for both CDquality and DVDquality inputs realizing in hardware a single MAC unit with 1 MAC/cycle capability and with a clock frequency below 10 MHz. The use of higher oversampling factors is still limited by the switching frequency of the power output bridge (see Section 3.6).
Finally, the bittrue arithmetic of the MAC hardware unit has been determined: using a 12bit fixedpoint data width the circuit complexity is greatly reduced versus a floating—point arithmetic implementation while the reduction of audio reproduction quality is negligible.
3.2. Noise Shaper
The most suited values for M and p depend on the time response of the used power MOS; the minimum impulse time should be comparable to the sum of T _{ r } and T _{ f }. As example for CDaudio signals, using , leads to a of 11 nanoseconds compatible with the timing of the selected power MOS devices [26].
3.3. Cross Point Estimator for NPWM
Simplified 2point estimators for NPWM, using linear interpolation (LI) or delta compensation ( ), allow a single chip implementation of the whole signal processing part. Here the crossingpoint is estimated using the firstorder formulas reported in Figure 5 requiring just 1 multiply/sample for and 1 division/sample for LI. Differently from [14, 15], where LI is preferred to in case of micropower speech amplifiers not using oversampling, our simulations prove that the THD reduction using NPWMLI or  is the same: a factor of 2 lower than UPWM. Thus, the use of C is preferred since it is less complex than LI requiring the computation of a multiplication/sample instead of a division/sample.
3.4. Multilevel PWM
A classic PWM has levels but also levels PWM and PWM techniques, up to 9 in [16], can be implemented. In 2state PWM the signal is switching between maximum and minimum supply voltage values, the two states and . Even for lowlevel signals binary modulation continuously provides energy to the LC filter and to the load. If the modulating input is null the PWM wave is still switching with a 50% duty cycle. The signal provided to the load is null but switching losses are paid thus reducing power efficiency. The 3state PWM signal switches between and 0 when the input signal is positive, otherwise between and 0. In case of null input there is no switching activity and hence switching losses are reduced. The 3state PWM modulator reduces by a factor 2 the voltage swing supported by the power MOS transistors allowing also the reduction of electromagnetic interference (EMI) and a better behaviour of the power devices. By further increasing the number of levels L the EMI and the switching losses can be further reduced. However while 2 and 3 levels PWM can be implemented with a single power MOS bridge, a PWM with levels require multiple power bridges, with matched behaviour. This increases remarkably the amplifier complexity and cost. Our analysis proves that for the complexity increase is not justified by a performance gain which is limited if compared to ternary PWM.
While the power output stage can be the same for 2 and 3 levels PWM, the digital circuitry is different. To generate a 2state PWM digital wave each pbit noise shaped and oversampled sample is compared to a digital sawtooth waveform. The 3state PWM modulator is realized using two 2state PWM modulators, one for positive input samples and the other for negative samples: after controlling the sign of each sample only one of the two 2state modulators is enabled. Although 3state PWM modulation doubles the cost of the 2state one the complexity of the whole system is comparable. Indeed, as shown in Section 4, the overall digital circuitry complexity is dominated by the noise shaping and oversampling filters which are common to 3 and 2state PWM. Summarizing 3 levels PWM is the best tradeoff between performance and circuit complexity.
3.5. Dead Time Insertion
3.6. Output Power Stage
3.7. Feedback Topologies
With respect to that adopted in A2, more complex mixedsignal feedback correction schemes have been proposed in literature [10, 18]. In these schemes the output PWM power signal, after attenuation and filtering, is converted in the digital domain through extra ADCs: 7bit flash ADC in [10] and 10bit SAR ADC in [18]. In the digital domain similar operations to those of A2 are carried out. These feedback schemes using ADC and operating in the digital domain have been also modelled. The achievable THD and sensitivity performances are slightly better than those of A2 while the hardware overhead is much higher: an attenuator, a filter and an ADC are required in the analog domain plus a digital correcting unit in the digital one. Being too complex the feedbacks schemes with ADCs are not considered in the comparison of Figures 9 and 10.
A simpler but effective feedback correction technique to reduce the amplifier sensitivity to parameter changes is derived from [21]: the sign of the output current provided to the load is used as 1bit control to check periodically which output transistor is on and to change consequently the inserted timeguard value. In [21] this technique has been proposed for the control of a 2state PWM powerbridge. In this work this approach has been redesigned to be integrated with oversampling, noise shaping, C cross point estimation and 3level PWM creating a new amplifier scheme: A3, 1bit feedback extension of the open loop A1. In our implementation we selected the value of 10 nanoseconds as resolution of correction for the PWM waveform.
With reference to max 70 Wrms delivered to a 4 speaker, Figures 9 and 10 compare the amplifier schemes A1, A2 and A3 in terms of power efficiency and THD. The maximum power efficiency, up to roughly 95% in Figure 9, is achieved by the open loop scheme A1. With such highefficiency each power MOS of the full bridge is dissipating less than 1 W avoiding extra cooling hardware. These results outperform classic DAC plus analog amplifier solutions: as example the hybrid analog scheme in [5] has a maximum power efficiency below 77%. The schemes with feedback topologies, A2 and A3, achieve similar efficiency, higher than 90%, only for power levels higher than 25–30 Wrms. Concerning THD, the lower distortion is achieved around 40–50 Wrms. The minimum THD is below the target of 0.2%; the use of feedback schemes allows reaching the target THD on a wider frequency range versus the open loop A1 scheme. Between A2 and A3 amplifiers the latter is preferred since it improves the THD and sensitivity performance of A1 but with minimal complexity overhead and minimal efficiency losses.
4. Prototyped Digital Audio Amplifier
From the design space exploration carried out in Section 3 the amplifier architecture, summarized hereafter, resulted as an optimal tradeoff between circuit complexity, power efficiency, output distortion and low sensitivity to parameter changes. The digital part includes: an oversampler by a factor using an Equiripple 4stage polyphase FIR interpolating filter, a cross point estimator based on C technique realizing a NPWM scheme, a noise shaper with output bits and a 5thorder noise shaping filter, 3level PWM generation, correction of PWM words through the insertion of time guard intervals also as a function of a 1bit signal feedback.
The digital processing part, implemented in HDL, has been synthesized in different CMOS standardcells technologies (90 nm 1 V supply voltage and 180 nm 1.8 V supply voltage) resulting in a digital complexity of 15.2 Kgates, mainly due to the noise shaping and interpolating filters. The low circuit complexity allows the fitting of the digital circuitry on several lowcost SRAMbased FPGA devices. As example the processing part of the amplifier occupies 90% of a Xilinx Virtex XCV100 or 58% of a Xilinx Spartan3 200. Such devices are available for large volume production at a cost of few dollars. Hence the low circuit complexity of the proposed architecture allows for a lowcost implementation. The power consumption for the above cited implementations is in the order of few hundreds of mW, as example 100 mW when integrating the amplifier in the XCV100 and playing 44.1 kS/s CDquality audio signals.
Summary of amplifier characteristics.
Design metric  Value  Test conditions 

Efficiency  94% at 45 Wrms  16bit 44.1 kS/s signal, 1 kHz tone 
THD  0.13% at 45 Wrms  
Pmax  70 Wrms  4 load 
5. Comparison to the State of the Art and Future Work
5.1. Comparison to the State of the Art
When compared to the state of the art of digital input power amplifiers our prototype stands for its lowcomplexity, while keeping high power efficiency and low THD levels. The distortion levels, THD below 0.2% at 1 kHz in the power range 35–60 Wrms with a minimum of 0.13% at 45 Wrms (see A3 in Figure 10), are suitable for audio HiFi applications. Other works in literature achieve lower THD values, as example in [13] the THD is 0.02% for similar power levels of 50 W, but at the expense of a lower efficiency and an increased complexity. The power efficiency is 80% in [13] while in our work is higher than 90%. The digital processing tasks in [13] require the use of multiple boards (1 DSP board for the digital audio processing plus 1 FPGA board for PWM processing) while our architecture just requires 1 lowcost FPGA having a bounded circuit complexity of 15 Kgates. The multiple boards digital amplifier in [13] features also a configuration with 90% power efficiency but with a THD of 0.2%. In [16] with a 9 level PWM inverter the achieved performances of 0.25% THD and 80% efficiency are worse than our results. This confirms our analysis in Section 3.4 that 3level PWM is the optimal choice for the output stage. Compact solutions using a single chip for the digital part, as in our work, and without heatsink have been proposed in [9, 19, 23, 31, 32]. However [19] is missing the feedback scheme needed, as proved in Section 4, against parameter changes; in [9] the efficiency levels are lower than those achieved by our scheme. The FPGAbased audio amplifier in [23] is missing feedback and NPWM techniques; it has a power efficiency of 80% and a THD of 1% both worse than our achieved results. In [31, 32] only the interpolation filter is implemented occupying a whole Spartan FPGA. With respect to our previous conference paper [20], where only UPWM is implemented and a lower oversampling factor and a lessperformance FIR interpolating filter are used, the audio processing system in this work has been improved including the digital techniques for NPWM, more accurate models for all the analog components, a more performing interpolating filter. The prototyped architecture in this work versus [20] achieves a much better THD value, predicted by the simulations and confirmed by measures on the prototype. Finally in some works [10, 17, 24], the shown results refer to simulations or prototypes only of the lowpower PWM generator without including a real prototyped power stage. As discussed in this work, and widely proved in literature, the nonideal behaviour of the power stage is a key issue in power audio amplifiers.
5.2. Future Work
The proposed platformbased approach has been used also to define the optimal architecture of digital power audio amplifiers using other complementary power MOS devices, such as the IR530 and IR9530. The achieved results with these MOS devices prove that, targeting a power level of 45 Wrms on an 8 load, optimal distortion performances below 0.2% can be reached in the range 17–35 Wrms with a power efficiency higher than 90%. The resulting architecture is similar to that discussed in Section 4 with the exception of the tuning of some parameters specifically optimized for the characteristics of the new power devices.
As work extension we are applying the same methodology to the design of a fully integrated digital input audio amplifier targeting maximum power levels of 12 W. Such amplifiers of few Watts are needed for batterypower terminals with audio playing capability [33, 34]. The design of the amplifier is carried out using an architecture similar to that in Section 4 fitted on a BCD 0.35 m technology providing CMOS transistors for the digital part and DMOS transistors for the analog power part. The only offchip circuit is the LC lowpass filter. Postlayout characterization proves that the digital amplifier can be integrated in less than 2 mm^{2}. The integrated power stage is an inverter with NDMOS sized with mm and m supporting, with low on of few m , output currents of 0.14 A on output load of 100 .
6. Conclusions
The design of digital audio power amplifiers is presented in the paper. A modelling platform has been built to allow a fast but still accurate exploration of the mixedsignal design space which involves the codesign of (i) audio processing algorithms with physical characteristics of hardware components and of (ii) lowpower integrated digital circuits with analog power devices. Different amplifier architectures have been modelled, simulated and compared to find optimal tradeoffs among different costfunctions: lowdistortion, high power efficiency, low circuit complexity and low sensitivity to parameter changes. The selected amplifier architecture has been prototyped, for power levels of tens of Watts, implementing the digital processing part on a single lowcomplexity FPGA while offchip components are used for the power output stage, no heatsink is required. The resulting digital amplifier, compared with the state of the art, features a low circuit complexity while keeping good power efficiency, higher than 90%, and lowdistortion levels, down to 0.13%. As future extension the realization of a fully integrated digital amplifier in BCD technology is presented for power levels of few Watts.
Declarations
Acknowledgment
The work has been partially supported by the SHAPES FP6 EU project.
Authors’ Affiliations
References
 Self D: Audio Power Amplifier Design Handbook. 4th edition. Newnes, Oxford, UK; 2006.Google Scholar
 Saponara S: Currentfeedback architecture for highslewrate and lowTHD highend audio amplifier. Electronics Letters 2008,44(25):14331434. 10.1049/el:20082660View ArticleGoogle Scholar
 Walker G: A class B switchmode assisted linear amplifier. IEEE Transactions on Power Electronics 2003,18(6):12781285. 10.1109/TPEL.2003.818825View ArticleGoogle Scholar
 Ginart AE, Bass RM, Leach WM Jr., Habetler TG: Analysis of the class AD audio amplifier including hysteresis effects. IEEE Transactions on Power Electronics 2003,18(2):679685. 10.1109/TPEL.2003.809330View ArticleGoogle Scholar
 Saponara S, Terreni P: Switchingbased topologies for highefficiency audio amplifiers. Proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS '05), 2005 1: 283286.Google Scholar
 Poulsen S, Andersen M: Hysteresis controller with constant switching frequency. IEEE Transactions on Consumer Electronics 2005,51(2):688693. 10.1109/TCE.2005.1468020View ArticleGoogle Scholar
 Hiorns RE, Sandler MB: Power digital to analogue conversion using pulse width modulation and digital signal processing. IEE Proceedings G 1993,140(5):329338.Google Scholar
 Botti E, Grosso A, Meroni C, Stefani F: Digital input audio power amplifiers in 0.6 μ m BCD technology: two examples. Proceedings of the IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD '04), 2004, Kitakyushu, Japan 16: 9396.Google Scholar
 Grosso A, Botti E, Stefani F, Ghioni M: A 250 W audio amplifier with straightforward digital inputPWM output. Proceedings of the European SolidState Circuits Conference (ESSCIRC '05), 2002 225228.Google Scholar
 Midya P, Roeckner B, Bergstedt S: Digital correction of PWM switching amplifiers. IEEE Power Electronics Letters 2004,2(2):6872. 10.1109/LPEL.2004.834795View ArticleGoogle Scholar
 Nielsen K: PEDEC—a novel pulse referenced control method for high quality digital PWM switching power amplification. Proceedings of IEEE Power Electronics Specialist Conference (PESC '95), 1998 200208.Google Scholar
 Saponara S, Fanucci L, Terreni P: Oversampled and noiseshaped pulsewidth modulator for highfidelity digital audio amplifier. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS '06), 2006, Nice, France 830833.Google Scholar
 Pascual C, Song Z, Krein PT, Sarwate DV, Midya P, Roeckner WBJ: Highfidelity PWM inverter for digital audio amplification: spectral analysis, realtime DSP implementation, and results. IEEE Transactions on Power Electronics 2003,18(1):473485. 10.1109/TPEL.2002.807102View ArticleGoogle Scholar
 Gwee BH, Chang JS, Adrian V: A micropower lowdistortion digital classD amplifier based on an algorithmic pulse width modulator. IEEE Transactions on Circuits and Systems I 2005,52(9):934949.Google Scholar
 Gwee B: Micropower lowdistortion digital pulse width modulator for a digital class D amplifier. IEEE Transactions on Circuits and Systems II 2002,49(5):113.Google Scholar
 Antunes VME, Silva JF, FernãoPires V: Experimental evaluation of a digital multilevel audio power amplifier. Proceedings of the IEEE Annual Power Electronics Specialists Conference (PESC '04), 2004 2: 11751179.Google Scholar
 Vlassopoulos N, Reisis D, Lentaris G, et al.: An approach for efficient design of digital amplifiers. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '06), 2006 55315534.Google Scholar
 Spectrum Design Solutions Inc : Digital audio solutions application brief. 2006.Google Scholar
 Apogee : Direct digital amplification (DDX) white paper. 2002.Google Scholar
 Saponara S, Terreni P: Mixedsignal design of a digital input power amplifier for automotive audio applications. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06), 2006 2: 212216.Google Scholar
 Jeong SG, Park MH: The analysis and compensation of dead time effects in PWM inverters. IEEE Transactions on Industrial Electronics 1991,38(2):108114. 10.1109/41.88903MathSciNetView ArticleGoogle Scholar
 Goldberg JM, Sandler MB: Pseudonatural pulse width modulation for high accuracy digitaltoanalogue conversion. Electronics Letters 1991,27(16):14911492. 10.1049/el:19910933View ArticleGoogle Scholar
 Liu YH, Teng JH, Hsieh CH: Design and implementation of a fullydigital, highefficiency classD amplifier system. Proceedings of the IEEE Region 10th Annual International Conference (TENCON '07), 2007, Taipei, Taiwan 14.Google Scholar
 Yoneya A: Pulse width and position modulation for fully digital audio amplifier. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), 2008, Seattle, Wash, USA 16921695.Google Scholar
 Saponara S, Nuzzo P, Nani C, van der Plas G, Fanucci L: Architectural exploration and design of timeinterleaved SAR arrays for lowpower and high speed A/D converters. IEICE Transactions on Electronics 2009, E92C: 843851.View ArticleGoogle Scholar
 Infineon Technologies : Data sheet BSO200N03S, Optimos 2 PowerTransistor. rev 1.6, 2008Google Scholar
 Cerezo J: Class D audio amplifier performance relationship to MOSFET parameters. International Rectifier AN 1070, 2005Google Scholar
 Philips : Data sheet UDA1320ATS. January 2000Google Scholar
 Turek D: Design of efficient digital interpolation filters for integer upsampling, M.S. thesis. MIT, Boston, Mass, USA; 2004.Google Scholar
 Benameur N, Loulou M: Design of efficient digital interpolation filters and sigmadelta modulator for audio DAC. Proceedings of the IEEE 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, (DTIS '09), 2008 17.Google Scholar
 Jacobsohn P, Palmer D: Audio sample rate conversion in FPGAs. Xcell Journal 2007, 5054.Google Scholar
 Huang X, Han Y, Chen L: The design and FPGA verification of a general structure, areaoptimized interpolation filter used in sigmadelta DAC. Proceedings of the IEEE International Conference on SolidState and IntegratedCircuit Technology (ICSICT '06), October 2006, Shanghai, China 21112113.Google Scholar
 Becker R, Groeneweg WH: An audio amplifier providing up to 1 Watt in standard digital 90nm CMOS. IEEE Journal of SolidState Circuits 2006,41(7):16481653. 10.1109/JSSC.2006.873674View ArticleGoogle Scholar
 Ryoo JY, Cho GH: A single chip l W CMOS audio power amplifier with pseudo buffer analog and class D switching mixed mode for mobile application. IEICE Transactions on Electronics 2005,E88C(9):18861892.View ArticleGoogle Scholar
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