A Platform-Based Methodology for System-Level Mixed-Signal Design

  • Pierluigi Nuzzo1Email author,

    Affiliated with

    • Xuening Sun1,

      Affiliated with

      • Chang-Ching Wu1,

        Affiliated with

        • Fernando De Bernardinis2 and

          Affiliated with

          • Alberto Sangiovanni-Vincentelli1

            Affiliated with

            EURASIP Journal on Embedded Systems20102010:261583

            DOI: 10.1155/2010/261583

            Received: 5 July 2009

            Accepted: 1 February 2010

            Published: 22 March 2010

            Abstract

            The complexity of today's embedded electronic systems as well as their demanding performance and reliability requirements are such that their design can no longer be tackled with ad hoc techniques while still meeting tight time to-market constraints. In this paper, we present a system level design approach for electronic circuits, utilizing the platform-based design (PBD) paradigm as the natural framework for mixed-domain design formalization. In PBD, a meet-in-the-middle approach allows systematic exploration of the design space through a series of top-down mapping of system constraints onto component feasibility models in a platform library, which is based on bottom-up characterizations. In this framework, new designs can be assembled from the precharacterized library components, giving the highest priority to design reuse, correct assembly, and efficient design flow from specifications to implementation. We apply concepts from design centering to enforce robustness to modeling errors as well as process, voltage, and temperature variations, which are currently plaguing embedded system design in deep-submicron technologies. The effectiveness of our methodology is finally shown on the design of a pipeline A/D converter and two receiver front-ends for UMTS and UWB communications.

            1. Introduction

            Modern electronic systems are becoming increasingly complex and heterogeneous. Telecommunication and multimedia applications require highly integrated, high-performance systems, where analog, RF, and digital components must be efficiently packaged into a single chip. Emerging sensor and actuator swarm applications, as well, demand customized mixed-domain systems to be embedded into a myriad of extreme physical environments to provide a variety of personal or broad-use services. On the other side, manufacturing technology is evolving deeper into the nanometer era, where leakage power, increasing process variations, reducing supply voltage, and worsening signal integrity conditions make it daunting even to assess the required performance specifications. To build future integrated systems, designers need to face several challenges, at all levels of abstraction, from system conception to physical implementation. Design complexity is indeed rising while, at the same time, time-to-market constraints are becoming tighter, and dependable systems need to be built out of increasingly unreliable components. Addressing the above challenges requires innovative solutions not only in manufacturing technologies and circuit architectures, but also in design methodologies and tools.

            A disciplined design style that reduces iterations in the flow should be based on a rigorous formalism leveraging accurate and robust performance modeling techniques to guarantee that performance variables of each component are correctly propagated across the design hierarchy. Moreover, fast, global optimization techniques need to be deployed to provide the best design options, for a given application, within a well-constrained and characterized search space. Finally, a practical framework should promote design reuse, and the separation of design concerns to reduce system complexity and boost designers' productivity.

            In this paper, we present a system-level design methodology for mixed-signal electronic circuits, which is inspired by the above principles, and leverages the platform-based design paradigm (PBD) [1, 2] as the natural formalization framework. In PBD, a platform is expressed as a collection of components and composition rules. A design is obtained by composing components of the platform in a platform instance. The refinement process consists of mapping a functional description into a set of interconnected components. The design space is systematically explored through a meet-in-the-middle approach in which top-down design constraints of the system are mapped onto bottom-up performance characterizations of the components in the platform library. Based on this paradigm, we provide a unified framework to assist designers at all levels of abstractions. At the system level, a global optimization technique provides the best design options by leveraging tradeoffs among all components, rather than composing systems using locally optimized components. At the component level, designs in different domains (e.g., RF, analog, or digital) can be concurrently characterized to provide an interface that offers smooth system integration while, at the same time, hiding implementation details. This orthogonalization of concerns allows making design decisions at the system level, where system tradeoffs can be evaluated across all RF, analog, and digital components. Moreover, the design process can be significantly shortened, because of the hierarchical approach enabled by our methodology, which progressively reduces the number of design variables. To ensure that reliable systems are produced, accurate and robust circuit performance models are crucial in our methodology, since high-level models should directly correspond to feasible physical implementations. Designs should therefore be robust to both modeling errors and process, voltage, and temperature variations (PVT), increasingly important as process parameters (minimum channel length, device threshold, supply voltage, etc.) decrease. As presented in [3], we include into our formulation techniques from design centering, traditionally adopted for digital design. With respect to [3], we add details on our performance models, in comparison with other modeling approaches, as well as on the mathematical derivation of the performance margin evaluation algorithm used in our robust optimization. Moreover, we apply our methodology to an additional example.

            This paper is organized as follows. Section 2 gives an overview of the PBD methodology applied to the analog and mixed-signal domains. In Sections 3 and 4, we discuss the robust system-level design problem and provide its mathematical formulation within the PBD paradigm. In Section 5, we illustrate our methodology using three case studies, namely, a pipeline A/D converter and two RF front-ends, for UMTS and UWB receivers. Finally, we draw some conclusions in Section 6.

            2. Analog Platform-Based Design

            Performing system-level design space exploration and optimization in a systematic way can have a great impact on system performance and cost. In a wireless receiver, for example, it allows distributing design requirements (e.g., gain, NF, linearity) among the chain building blocks, and early evaluation of several tradeoffs, such as preselect filter selectivity and power consumption versus front-end linearity, or base-band filter selectivity versus ADC resolution.

            In traditional analog and mixed-signal design flows, experienced architects conduct system-level design, and system specifications are empirically partitioned among the various functional blocks that circuit designers have to implement. In fact, since an effective system-level optimization is not achievable without accurate knowledge of the achievable performance of the several building blocks, final system performance may largely deviate from the expected one, which can result in silicon respins. To simultaneously achieve high-quality system integration starting from accurate circuit characterizations, analog-PBD (APBD) has been proposed and formulated in [47] as a meet-in-the-middle recursive process consisting in top-down optimization (platform mapping) and bottom-up characterizations, exporting the feasible design spaces of platform components to higher levels of abstraction.

            Optimization is performed on behavioral models, that is, mathematical representations of electronic circuits, capturing their functionality as a function of a set of input, output, and configuration parameters. To allow information hiding and intellectual property (IP) protection, a feasible performance model is also provided for each circuit block, which exports the performance achievable by any available implementation of the block (in the platform library), without propagating implementation details. Performance models are built in a characterization process, as described in Section 2.1. Both models are accompanied by validity laws, that is, a set of constraints and inequalities delineating the validity regions of all component models and their compositions. An Analog Platform (AP) is therefore a library of components, each one decorated by the above set of models and laws. A design is a platform instance, that is, a correct composition of elements, implementing the desired function and, at the same time, optimizing a set of quality metrics.

            2.1. Analog Performance Models

            Performance models play a critical role in analog system-level design and particularly in platform-based design. Performance models are used to constrain the optimization process to achievable performances within the considered architecture space. Therefore, system-level design approaches have to consider the nature of performance models explicitly during system optimizations.

            In the recent few years, a number of papers have appeared on the generation of performance models [8, 9] and even direct modeling of the feasibility region [10, 11]. The latter set of works aims at providing a classifier that separates feasible n-tuples of performances from unfeasible ones, without recurring to a regression-based approach. From the system-level perspective, feasibility models allow casting exploration problems in a more intuitive performance space rather than mapping down to implementation parameters. The number of variables in the optimization problems is consequently reduced (at least in nondegenerate cases) and architecture selection becomes readily available as different implementation topologies may share common performance spaces.

            There are two basic model generation schemes, equation based and simulation based (Figure 1). The first approach requires deriving analytical expressions to estimate performance from configuration (regression case) or to model the performance space (classification case). The second approach is based on statistical approximation techniques, where a set of performance samples is evaluated and exploited to build a performance model approximation. In order to compare the different schemes, it is useful to introduce some figures of merit for performance models. The cost of generating a performance model can be decomposed into different contributions: model setup, model generation, and model retargeting. In particular, the first two contributions are usually at odds and need to be traded off in real models. Another fundamental figure of merit is accuracy. Accuracy is usually assessed through some function (e.g., average or maximum) of the estimation error. We can further distinguish between two different kinds of error, the error on the training data and the generalization error. The last figure of merit we consider is generality of the approach, both in terms of classes of circuits and of the performance figures that can be captured. Analytical- and simulation-based models are at opposite ends of the spectrum of performance model schemes.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig1_HTML.jpg
            Figure 1

            Equation-based and simulation-based approaches for generating performance models compared with multiple metrics. The 0–10 axes encode the difficulty of each figure of merit.

            Analog platform performance models rely on Support Vector Machines (SVMs) as a way of approximating the classifier http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq1_HTML.gif discriminating the feasible performance space. Given a set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq2_HTML.gif of simulated performance vectors (as detailed in [10]), SVM training selects a subset of vectors http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq3_HTML.gif (support vectors) and corresponding weight coefficients http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq4_HTML.gif so that the classifier function is obtained as

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ1_HTML.gif
            (1)
            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq5_HTML.gif is a biasing term (also determined during training) and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq6_HTML.gif is an SVM parameter. As schematically shown in Figure 2, a set of design configurations (e.g., transistor size for the input differential pair and its bias current) is generated as points in the configuration parameter domain http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq7_HTML.gif . Electrical simulation maps these points into vectors in the performance space http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq8_HTML.gif . SVMs are then used to classify the simulated points and generate a feasible performance model. Performance vectors http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq9_HTML.gif are obtained through simulation, so that maximum generality is available in terms of allowable circuits and performance figures. Moreover, SVMs can be generated so as to minimize the impact of false positives, that is, unfeasible performances classified as feasible. In fact, several case studies have shown that the approximation around support vectors is usually restricted in small regions, so that optimal predicted performances are very close to some actually simulated performance vectors. This is an amenable feature to enable effective hierarchical design with minimum risk of incurring in iterations and redesign.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig2_HTML.jpg
            Figure 2

            Schematic view of the performance model generation for a simple differential amplifier.

            3. Robust System-Level Design

            Robust design and optimization have traditionally been closely related subjects. In fact, it is almost impossible to consider an aggressive optimization scheme without considering the robustness of the achieved solutions. System-level design should embrace robust approaches for two separate reasons. From the system level, mixed-signal design has to cope with model inaccuracies that are intrinsic to the behavioral models exploited in design explorations. The more complex the system, the larger the hierarchical structure of the design and the higher the risk when performing nominal design optimizations. In fact, composition of high-level models may provide results whose accuracy is not easily bounded, so either a costly iterative scheme between top-down system-level design and bottom-up verification or relaxed (robust) constraint propagation is adopted. From the implementation level, any performance model is subject to two kinds of inaccuracies: intrinsic modeling errors and process variability. While some control is available on the former source (even if potentially very expensive or restrictive), the latter cannot be solved with deterministic approaches.

            Early approaches to computer-aided design centering in an analog context date back to the early 80s [1214]. All the approaches have a common dependency on the model used to estimate performance degradation on design parameters and, if yield is actually considered, on joint probability functions used to compute yield expectations. However, robust optimization for analog design has not been developed at the same level as nominal optimization. The largest obstacle on the way is represented by the complexity of the resulting optimization problem, which is usually captured as a semiinfinite programming problem. In [15], a circuit optimizer based on simulation is enriched with robust design features, showing significant improvements albeit constrained with scaling issues for complex circuits. The lesson learned from early attempts of including process variations and mismatch in automated circuit design is the tremendous complexity of the resulting problem.

            Models generated with classic approaches based on Response Surface Methodology (RSM) [16] can become too expensive to build because of the number of primal parameters and the complexity of the necessary simulations. Instead, we propose an alternative approach, based on approximate models to be developed at the system level.

            3.1. Previous Approaches

            Several robust approaches to analog design have been proposed during the past few years. Far from being exhaustive, we review those ones that we consider more relevant to the approach presented in this paper (Figure 3). Initially, relaxation of system constraints during top-down optimizations was exploited as an attempt to overcome poor architecture models. We can date back the first rigorous attempt in this direction with the top-down constraint-driven methodology presented in [17] and demonstrated in [18, 19]. Since in pure top-down approaches no detailed information is available on implementation as architectures have not been selected in the first design steps, the methodology formulates the optimization problem (constraint propagation problem) as the maximization of a set of flexibility functions. Flexibility functions are introduced to capture the complexity of implementing a specific set of performances. Therefore, in place of optimizing for power or area, the optimization problems maximize the "flexibility" of achieving the optimum set of performances (i.e., minimize the "effort" of implementation). Albeit rigorously formulated, the methodology was rather limited in performing aggressive optimizations because of the halo inherently inserted by the heuristic flexibility functions.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig3_HTML.jpg
            Figure 3

            Main approaches to robust system-level analog and mixed-signal design in the last few years.

            More recently AMGIE [20] proposed to carry out hierarchical design via a set of optimization problems where, at each abstraction level, component performances are bounded to predefined ranges. A robust approach is achieved inserting margins http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq10_HTML.gif on all performances, so as to compensate for modeling inaccuracies. However, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq11_HTML.gif has to be determined a priori so that its final value is not the result of an optimization problem. In particular, the cost of meeting the margin on performances is not traded off with the potential improvements in system performances, that is, the sensitivity of the goal function on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq12_HTML.gif is not evaluated at all, leaving a wide discretionality in determining performance margins.

            Recent advances in convex optimization [21] have revitalized analytical approaches to analog design and, consequently, robust design. ROAD [22] introduces a robust optimization approach based on posynomial performance models. To improve accuracy, a simulator-in-the-loop approach is selected and local posynomial models are generated around design points. It is then possible to deal with nonconvex design spaces exploiting the possibility of exactly solving large-scale convex programs. OPERA [23] introduces a robust geometric optimization problem to maximize yield over statistical variations. Design process variations are captured with confidence ellipsoids and approximated to yield a convex problem. The robust design formulation computes optimal design parameters to meet a predetermined yield target. Convex optimization approaches, however, tend to limit designers in selecting cost function and formulating their problems. The efficiency achieved in actually solving the problem may be then counterbalanced by the effort required to model the system and validate the analytical expressions used to set the problem. Moreover, classic approaches to system design with convex optimization are based on generating a flat optimization problem, where all circuit topologies have been selected, thus setting a challenging problem as system complexity grows and mixed-signal designs are approached.

            Recently, a hierarchical approach to robust system-level analog design has been presented [24]. Performance centering is sought through concurrent maximization of system-level flexibility based on behavioral models and implementation-level performance margins based on performance models. A possible limitation of the approach is the requirement of posynomial models to capture both system-level and implementation-level constraints. While this assumption is certainly acceptable for some classes of analog systems, it may be in practice a hard one to satisfy as it becomes increasingly difficult to guarantee (or even assess) model convexity as design hierarchy becomes deeper and high-level behavioral models are exploited in mixed-signal design space explorations.

            In our framework, we extend the hierarchical approach by removing the posynomial constraints on design formulation. As in [23, 24], robustness is achieved through maximization of margins with respect to system specifications. Extending the approach to analog platforms, we obtain a two-fold advantage. First, very accurate performance models (not constrained to be convex, posynomial, or even in explicit form) can be exploited to estimate implementation margins. It is then possible to accurately weigh implementation margins since model inaccuracies are kept to minimum levels. Second, arbitrary system behavioral models and constraints can be used to formulate the optimization problem since analog platform-based design relies on global stochastic optimization approaches to find optimal implementations. Designers can then specify their systems without recurring to posynomial approximations and capturing arbitrary nonconvex constraints.

            4. Mathematical Formulation

            The essence of APBD in its general formulation is pictorially represented in Figure 4 and consists of a bottom-up platform generation phase, where architectural constraints are characterized and exported to higher levels, and a top-down optimization phase, where system constraints are intersected with architectural constraints and the system cost is minimized. At the end of the optimization, system specifications are mapped on the available platform library and the process is repeated.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig4_HTML.jpg
            Figure 4

            Platform mapping optimization process from level (denoted as application in this case) to level (denoted as architecture ).

            4.1. Nominal Optimization

            In a nominal formulation, the optimization process mapping platform http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq15_HTML.gif onto platform http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq16_HTML.gif is mathematically captured as

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ2_HTML.gif
            (2)
            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq17_HTML.gif is a set of system performance indices, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq18_HTML.gif is a set of platform configuration parameters, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq19_HTML.gif is the behavioral model used to map http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq20_HTML.gif into http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq21_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq22_HTML.gif represents the set of constraints imposed on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq23_HTML.gif by system specifications, and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq24_HTML.gif captures the set of constraints on the configuration parameters http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq25_HTML.gif imposed by the architecture space. The set of constraints in (2) can be visualized defining two sets in the optimization space. The system constraints http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq26_HTML.gif define the set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq27_HTML.gif of feasible performances from the system perspective. The architectural constraints http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq28_HTML.gif define, through the behavioral model http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq29_HTML.gif , the set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq30_HTML.gif of achievable performances with the current architecture (platform). Figure 5 shows a pictorial representation of the two sets and how mapping is the minimization of the cost function on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq31_HTML.gif . Nominal design optimization computes the vector http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq32_HTML.gif that produces the minimum cost in (2). At optimum, the Karush-Kuhn-Tucker conditions require for active constraints that http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq33_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq34_HTML.gif , which means that the optimized system is, in general, at the "edge" of implementability on several constraints from both a system and an architecture perspective. However, any modeling error in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq35_HTML.gif may translate in actual performances http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq36_HTML.gif (computed with accurate models) to violate http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq37_HTML.gif . Similarly, any modeling error in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq38_HTML.gif may translate in platform http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq39_HTML.gif performances being unfeasible. When similar events occur, system design needs either to be iterated or degraded performances have to be accepted. Degradation may be rather severe and force costly redesigns when aggressive specifications are addressed. Even accurate models may fail if performance degradation is due to process parameter dispersion or temperature variation. In general, it is deemed unfeasible to export this information with performance models as for each circuit configuration http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq40_HTML.gif a function has to be provided http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq41_HTML.gif which computes the probability density function of performance http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq42_HTML.gif given the circuit sizing http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq43_HTML.gif . As the approximation of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq44_HTML.gif usually relies on expensive Monte Carlo simulations around http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq45_HTML.gif , the generation of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq46_HTML.gif over the entire configuration space http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq47_HTML.gif is hardly doable.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig5_HTML.jpg

            Figure 5

            4.2. Robust Optimization

            To address this problem, an alternate formulation of the optimization problem is required. The sets of constraints http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq48_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq49_HTML.gif have to be satisfied with some margin so as to compensate for modeling inaccuracies. We can write the new set of constraints as http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq50_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq51_HTML.gif . Margins have an intuitive interpretation, defining a sphere (as defined by the norm adopted) http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq52_HTML.gif for system constraints and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq53_HTML.gif for performance constraints around the optimal pair http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq54_HTML.gif . The objective of the optimization problem is then changed so as to maximize margins http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq55_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq56_HTML.gif , which corresponds to the maximization of the volumes of the spheres around the optimum configuration and performance points. The original cost function is inserted as an added constraint with a dedicated http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq57_HTML.gif . Given a minimum cost target http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq58_HTML.gif , at optimum http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq59_HTML.gif is maximized constrained on the other margin variables, so that a tradeoff is evaluated between cost value and robustness during the optimization. Therefore, problem (2) becomes

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ3_HTML.gif
            (3)

            System-level constraints are usually available in explicit form; therefore http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq60_HTML.gif can be immediately written as

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ4_HTML.gif
            (4)

            and included in the optimization problem. Additional constraints may be inserted to set specific relations on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq61_HTML.gif , for example, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq62_HTML.gif . The problem is more involved with performance models, as analog platforms provide http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq63_HTML.gif in implicit form with a nonlinear function http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq64_HTML.gif . In this case, we interpret the margin http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq65_HTML.gif in the following way. For a performance model http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq66_HTML.gif , its frontier http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq67_HTML.gif defines the boundary of the feasible region. Given a configuration point http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq68_HTML.gif satisfying performance constraints http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq69_HTML.gif , its margin http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq70_HTML.gif can be obtained finding the closest configuration http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq71_HTML.gif to http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq72_HTML.gif and computing the norm of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq73_HTML.gif . If all components http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq74_HTML.gif of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq75_HTML.gif have the same weight, then http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq76_HTML.gif (the performance constraint http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq77_HTML.gif is consistent with the formulation in (2) as it is equivalent to the argument of sgn in (1) being http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq78_HTML.gif after a sign change). In this case, minimizing http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq79_HTML.gif is equivalent to maximizing the volume of the sphere around http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq80_HTML.gif that is enclosed in the feasible space (within its boundary http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq81_HTML.gif ). The general case of different weights on different performance components can be immediately obtained adopting a different norm when computing http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq82_HTML.gif . Since the different performances in the performance vectors used to generate http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq83_HTML.gif can differ in orders of magnitude, they are all preconditioned to be normalized in the interval http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq84_HTML.gif . In the following paragraph, we show how to compute http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq85_HTML.gif based on the SVM representation of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq86_HTML.gif .

            4.3. Performance Margin Evaluation

            The problem of finding http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq87_HTML.gif given http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq88_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq89_HTML.gif is analogous to the problem of finding the largest hyperellipsoid enclosed by http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq90_HTML.gif . Initially we start solving the case of hypersphere enclosure, extending to the general case at the end of this paragraph. By definition, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq91_HTML.gif is the point on the boundary http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq92_HTML.gif which shows minimum distance from http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq93_HTML.gif . To simplify notation, we set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq94_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq95_HTML.gif . Therefore, we can obtain http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq96_HTML.gif solving the following optimization problem:

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ5_HTML.gif
            (5)

            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq97_HTML.gif is implicitly defined from (1) as

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ6_HTML.gif
            (6)

            The optimization problem obtained substituting (6) into (5) is evidently nonlinear and can be interpreted as vector projection onto a nonconvex set. In fact, while the cost function in (5) is strictly convex, the equality constraint in (6) is nonlinear (and nonconvex). At optimum, the Karush-Kuhn-Tucker conditions require that

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ7_HTML.gif
            (7)

            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq98_HTML.gif is the Lagrange multiplier, the first equation states the feasibility condition for http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq99_HTML.gif , and the other equations enforce that the gradient of the Lagrangian function http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq100_HTML.gif vanishes at any optimal point. System (7) originates from the equivalent problem obtained by (5) after squaring the cost function. For each http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq101_HTML.gif , the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq102_HTML.gif th component of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq103_HTML.gif can therefore be computed as follows:

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ8_HTML.gif
            (8)

            By substituting (6) into (8), for each http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq104_HTML.gif , we finally obtain the equations in (7).

            The nonlinear system (7) can be solved with Newton-Raphson (NR) providing quadratic convergence if http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq105_HTML.gif is "close" to http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq106_HTML.gif . http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq107_HTML.gif is therefore the radius of the largest hypersphere enclosed in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq108_HTML.gif . However, the nonlinear nature of (7) generates two problems. First, a multitude of solutions may exist, so we could achieve convergence on a point on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq109_HTML.gif which is not the closest to http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq110_HTML.gif ; second, NR may not converge at all if a sufficiently good initial guess is not provided. To cope with the above problems we first adapt to our problem a more sophisticated implementation of the NR method, similar to the damped Newton's method [21], which tries to improve on basic NR poor global convergence. Then we add some ad hoc heuristics to generate a good initial guess.

            Solving for http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq111_HTML.gif one of the equations in (7) and substituting the result into the other equations, we obtain an http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq112_HTML.gif -dimensional system in the unknown vector http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq113_HTML.gif , which can be denoted as http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq114_HTML.gif . We then combine NR method with the minimization of the function http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq115_HTML.gif , in the sense that we accept the solution provided by each NR step only if the step considerably reduces http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq116_HTML.gif . If this does not happen, we backtrack along the NR direction http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq117_HTML.gif starting from the old point http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq118_HTML.gif until we have an acceptable new point http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq119_HTML.gif ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq120_HTML.gif ). Since the NR step is a descent direction for http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq121_HTML.gif , we are guaranteed to find an acceptable point by backtracking. The backtracking routine is based on the line minimization rule [25, 26] and consists in defining http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq122_HTML.gif , as the restriction of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq123_HTML.gif along http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq124_HTML.gif , and finding http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq125_HTML.gif so as to minimize http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq126_HTML.gif . To save on the number of function evaluations, a cubic approximation of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq127_HTML.gif is actually computed based on available information on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq128_HTML.gif and its derivative. Since the improved NR method can still occasionally fail converging on a local minimum of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq129_HTML.gif , we can try a new starting point according to the following heuristics:

            (i)we compute the distance along reference axes in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq130_HTML.gif using bisection-based monodimensional methods. It is then possible to bound the distance of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq131_HTML.gif . We observed that in practical cases whenever this bound is smaller than some http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq132_HTML.gif (whose actual value depends on normalization of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq133_HTML.gif ) convergence is always achieved and the correct http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq134_HTML.gif is returned by Newton-Raphson,

            (ii)we set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq135_HTML.gif to start iterations as we expect http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq136_HTML.gif to define a relatively "thin" feasible space. Whenever the previous heuristics is not satisfied, we run http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq137_HTML.gif NR iterations perturbing the initial point http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq138_HTML.gif in the direction of the axis where the minimum distance has been found in the previous point (iterations are aborted after a predetermined number) until the minimum distance solution is reached. We observed that http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq139_HTML.gif is generally sufficient to achieve convergence,

            (iii)in case of nonconvergence, we return the bound computed in the first point. In practice, there is no consequence in doing this because it always happened for points deep in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq140_HTML.gif in our tests.

            The above procedure can be extended to hyperellipsoids enclosure by scaling http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq141_HTML.gif with a unitary matrix http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq142_HTML.gif to obtain http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq143_HTML.gif and extending the previous approach on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq144_HTML.gif . Margins found in this way need to be scaled back to the initial space through http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq145_HTML.gif . This allows selecting different margins on different performances.

            The overall algorithm complexity has been computed to be http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq146_HTML.gif where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq147_HTML.gif is the number of performance figures in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq148_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq149_HTML.gif is the number of performance vectors, and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq150_HTML.gif is the cost for evaluating the exponential function as in (1).

            5. Examples

            In this section we apply the previous results to the case studies reported in [4, 27, 28]. The original designs are reformulated according to (3). The selection of good cost functions is a crucial issue in system-level optimization, with implications that may become subtle when maximizing robustness. In our experiments, we used the following cost prototype:

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ9_HTML.gif
            (9)

            A few considerations may help explain the form of (9). First, the volumes of the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq151_HTML.gif ellipsoid and the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq152_HTML.gif hypercube increase with number of dimensions for constant margin; therefore an overall normalization is achieved with the powers http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq153_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq154_HTML.gif of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq155_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq156_HTML.gif products. As far as architecture margins are concerned, we can partition http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq157_HTML.gif , where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq158_HTML.gif refers to the single platform component. Elements http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq159_HTML.gif of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq160_HTML.gif are strongly related describing an ellipsoid embedded in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq161_HTML.gif . Therefore a single element is sufficient to describe the margin of the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq162_HTML.gif th component. If we consider that the composition of blocks is as robust as the weakest block, we can obtain a different cost function considering http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq163_HTML.gif . The http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq164_HTML.gif function is used to saturate the sensitivity on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq165_HTML.gif as margins too wide may cause degenerate robustness/performance tradeoffs. Finally, if we analyze the Pareto optimal curves as a function of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq166_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq167_HTML.gif , we can easily obtain that the relative importance of two http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq168_HTML.gif parameters is controlled by

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ10_HTML.gif
            (10)

            so that http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq169_HTML.gif sets the relative impact of variations of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq170_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq171_HTML.gif . When http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq172_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq173_HTML.gif are considered, we obtain (for small http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq174_HTML.gif )

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ11_HTML.gif
            (11)

            which makes it clear how the parameter http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq175_HTML.gif can be used to control sensitivity on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq176_HTML.gif without recurring to exponent ranges that may generate numerical issues during optimization. Equations (10) and (11) can be used as guidelines to set parameters in (9), as exemplified in the following case studies.

            As a final remark, we notice that architecture performance margins are taken on lower-dimensional models than the corresponding platform ones. In fact, some parameters are simply "ancillary" parameters required for correct composition of platform models, and as such not related with the robustness of the solution. One other parameter, which we did not include when computing margins at the component (architectural) level, is power. Power may be considered as an annotation on circuit performances. In fact, in our case studies, if a given circuit exhibits a larger (or smaller) power consumption with respect to the estimated one, it does not affect circuit performances (which is obviously not true if gain is not met, for example). We remark that this is an arbitrary design choice and is not related to the presented methodology. On the other hand, in our examples we introduce margins on power at the system-level to trade the global power consumption with the robustness of the solution. Also, area has not been exploited as a robustness criterion, but this can be seamlessly introduced in the robust optimization scheme to export at the system level area penalties involved in topology selection.

            5.1. Pipeline ADC

            In [4] we performed design space exploration of a 14-bit, 80 MS/s pipeline analog-to-digital converter (ADC) in 0.13  http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq177_HTML.gif m, 2.5 V analog supply CMOS technology. The simplified block diagram of the system is represented in Figure 6. The ADC is made up of 4 multibit stages and includes digital calibration circuits to enhance performance. In particular, the digital-to-analog subconverter (DAC) errors are canceled with the DAC Noise Cancelation (DNC) technique [29] and the first-stage Sample-and-Hold Amplifier (SHA) errors are corrected through a Gain and Distortion Error Correction (GDEC) algorithm as in [30]. The SHA gain and third-order distortion coefficients, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq178_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq179_HTML.gif , are first estimated from the digital back-end by a PolyEstim circuit. At the same time the distorted SHA characteristic is effectively inverted (rectified) by the PolyInv circuit. As shown in Figure 7, the interstage residue amplifiers are fully differential switched capacitor systems (FB C in Figure 6) implemented with a telescopic Operational Transconductance Amplifier (OTA). Loading effects and switches nonidealities are also included in the model. The OTA optimization needs to be performed under the hypothesis of operation of digital calibration circuits, as detailed in [5]. In order to perform efficient high-level exploration across the analog/digital boundary while reducing the complexity of the problem we provided characterizations and feasible performance models for the main blocks, that is, the digital calibration logic and the first-stage residue amplifier. The remaining part of the converter was considered ideal. Indeed, the first stage in a multibit pipeline ADC is the most critical block since the accuracy required in terms of gain and linearity is maximum; the remaining stages have been lumped into one block in our macromodel. Since the first stage provides the first 4 bits, a nominal gain http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq180_HTML.gif of 8 is required to the SHA. However, the presence of the digital correction circuit relaxes this constraint enabling power savings. In the nominal optimization, the cost function aims at minimizing power consumption http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq181_HTML.gif of the overall ADC subject to performance models and minimum system requirements on DNL, INL, and the signal-to-noise ratio (SNR) due to thermal noise. The architectural space includes four correction algorithms to invert the polynomial nonlinearity corresponding to different accuracy and power consumption levels, based on [5]. Performances are evaluated through the behavioral model http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq182_HTML.gif of the mixed-signal platform library, in which each component is embedded.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig6_HTML.jpg
            Figure 6

            Pipelined converter simplified block diagram—feasible performance models have been generated for the blocks in green: the SHA and the gain error digital calibration block (GDEC).

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig7_HTML.jpg
            Figure 7

            Single-ended equivalent (simplified) circuit of the switched capacitor SHA.

            The extension to the robust approach of the optimization problem has been achieved through the following formulation, based on the cost template in (9):

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ12_HTML.gif
            (12)

            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq183_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq184_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq185_HTML.gif , and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq186_HTML.gif are system margins on power, DNL, INL, and SNR, respectively. http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq187_HTML.gif , the architecture margin, is normalized in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq188_HTML.gif and is computed by exploiting an ellipsoid in which weight for the OTA bandwidth (BW) and open-loop gain ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq189_HTML.gif ) is 2 times the other performance indices. The parameter http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq190_HTML.gif controls cost function sensitivity on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq191_HTML.gif , hence the architecture margin on the optimum.

            Several optimizations with different cost parameter values were efficiently performed through simulated annealing, with an average time of 13 hours per run. Three meaningful results are reported in Table 1 to demonstrate how the tradeoffs between system margins (especially http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq192_HTML.gif on power) and architecture margins (especially on gain and bandwidth) can be thoroughly explored within our methodology. In ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq193_HTML.gif ) more emphasis has been given to the architectural constraint margins, setting http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq194_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq195_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq196_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq197_HTML.gif thus obtaining higher http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq198_HTML.gif values (e.g., up to 27% on bandwidth). On the other hand, in ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq199_HTML.gif ) and ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq200_HTML.gif ) focus is more on system margin maximization. For example, in ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq201_HTML.gif ) by setting http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq202_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq203_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq204_HTML.gif , and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq205_HTML.gif we got a 17% margin on bandwidth. This lowers down to 0.8% in ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq206_HTML.gif ) where we set http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq207_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq208_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq209_HTML.gif , and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq210_HTML.gif thus obtaining the overall minimum power solution.
            Table 1

            Performance of optimal ADC, OTA, and GDEC circuit for 3 different cost functions. http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq211_HTML.gif denotes the system and architecture margins.

            Performance

            ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq212_HTML.gif )

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq213_HTML.gif

            ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq214_HTML.gif )

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq215_HTML.gif

            ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq216_HTML.gif )

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq217_HTML.gif

            DNL (LSB)

            0.07

            0.73

            0.04

            0.76

            0.07

            0.73

            INL (LSB)

            0.43

            0.57

            0.04

            0.96

            0.45

            0.55

            SNR (dB)

            85.1

            9.1

            85.1

            9.1

            82.6

            6.6

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq218_HTML.gif (mW)

            57.1

            42.9

            59.6

            40.4

            42.6

            57.4

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq219_HTML.gif (mW)

            52.8

            55.3

            37.8

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq220_HTML.gif

            194

            134

            267

            88.7

            228

            2.72

            BW (KHz)

            4269

            1119

            3768

            739

            2755

            22.7

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq221_HTML.gif

            7.46

            7.65

            7.24

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq222_HTML.gif (mW)

            4.2

            4.2

            4.8

            We notice how in lower-power designs the system-level margin on SNR tends to decrease as well. Moreover, the unity gain frequency (and the bandwidth), which is the key parameter influencing the settling behavior of the SHA, tends to decrease thus impacting the accuracy of the system (i.e., INL, DNL, and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq223_HTML.gif ) and mandating more accurate and power expensive calibration circuits. We finally compare results in Table 1 with the optimal design reported in [4]. Using a nominal optimization technique, we obtained 52.5 mW ADC power consumption with approximately 9% margins. This implies that, in the nominal formulation, it was still possible to obtain reasonable architectural and system margins by acting both on optimization constraints and feasible performance model generation constraints as viable safety margin knobs. However, we had not chances to quantitatively explore and efficiently control the involved performance/margin tradeoffs as we have demonstrated here in the robust formulation.

            5.2. UMTS Front-End

            In this and the following subsections, we demonstrate our methodology on RF systems. We start with robust optimization of the UMTS receiver front-end presented in [27]. The receiver consists of a Low-Noise Amplifier (LNA) and a mixer for a direct conversion UMTS receiver. All components were characterized and embedded in a platform library. In the nominal optimization, the cost function aims at minimizing power consumption of the overall receiver subject to compliance of standard UMTS tests and performance models. The architecture space is formed by two LNA topologies and one direct-conversion mixer, as reported in Figures 8, 9, and 10. The system-level constraints (directly derived from UMTS specifications) are compactly formulated with
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ13_HTML.gif
            (13)
            where http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq224_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq225_HTML.gif are the output-referred second- and third-order distortion powers, respectively, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq226_HTML.gif the output-referred noise power, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq227_HTML.gif the output-referred power due to reciprocal mixing, and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq228_HTML.gif the front-end gain. The standard specifies the conditions in which system performance has to be assessed. All quantities are evaluated through the receiver behavioral model http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq229_HTML.gif , described in [27]. Exploiting the robust formulation (3) and the cost function template (9), the following robust optimization problem has been obtained:
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ14_HTML.gif
            (14)
            The parameter http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq230_HTML.gif has been used to control the amount of margin on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq231_HTML.gif and thus the architecture margin at optimum. The http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq232_HTML.gif term has been set as to saturate at margins larger than 15% ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq233_HTML.gif is normalized in http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq234_HTML.gif ). http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq235_HTML.gif determines power consumption margin and its weight is controlled by the parameter http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq236_HTML.gif . http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq237_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq238_HTML.gif set the margin on minimum interference requirements. Since in a direct conversion receiver second-order terms are crucial, we increased its weight squaring http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq239_HTML.gif . Finally, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq240_HTML.gif measures the mismatch on the interface capacitance between LNA and mixer, and has to be minimized, as detailed in [27] in order to guarantee correct platform composition.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig8_HTML.jpg
            Figure 8

            Schematic for the n-type input stage LNA used in the UMTS receiver front-end.

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig9_HTML.jpg
            Figure 9

            Schematic for the np-type input stage LNA used in the UMTS receiver front-end.

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig10_HTML.jpg
            Figure 10

            Schematic for the mixer used in the UMTS receiver front-end.

            An optimization trace projected onto the Power-NF plane for the LNA is reported in Figure 11. The robust approach is able to perform architecture selection between the LNA topologies, as shown in Table 2. Larger values for the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq241_HTML.gif parameter allow more aggressive optimizations, as shown by lower-power consumption levels. Moreover, it is evident that the optimal point does not lie on the Pareto optimal curve of the LNA performances, as was the case in the nominal design in [27]. In this example, area occupation is not directly traded with system robustness against variations. Table 2 shows the performances at optimum together with the main performance indices and corresponding margins. In this case, since direct conversion architectures are extremely sensitive to second-order distortion, we exploited an ellipsoid to compute http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq242_HTML.gif so that the second-order distortion coefficient weight is 3 times the other performance indices. Overall, compared to the optimal nominal design, a significant increase in power is observed (+32% for the case http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq243_HTML.gif ), but the final system allows for wide margins to compensate modeling inaccuracies and layout effects.
            Table 2

            UMTS receiver robust optimization results as a function of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq244_HTML.gif . Larger values of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq245_HTML.gif decrease the sensitivity on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq246_HTML.gif in (9). Note that the LNA topology is also affected by robust optimizations.

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq247_HTML.gif

            nom.

            0

            0.1

            0.3

            Gain (dB)

            30.8

            29.9

            31.2

            27.7

            Power (mW)

            10.9

            14.4

            12.9

            11.7

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq248_HTML.gif (dBm)

            −99.1

            −99.7

            −100.2

            −99.5

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq249_HTML.gif (dBm)

            −98.7

            −99.5

            −100.3

            −99.7

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq250_HTML.gif

            0.7/3.5

            1.2/4.3

            0.5/3.7

            NF (dB)

            6.8

            6.9

            6.4

            6.9

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq251_HTML.gif (dB)

            18.2

            15.4

            17.3

            15.7

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq252_HTML.gif (dB)

            3.5

            3.8

            4.5

            5.8

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq253_HTML.gif (mW)

            5.7

            7.3

            6.1

            4.2

            Topology

            n

            n

            n

            np

            Margin

            1.3%

            12.5%

            6.9%

            3.6%

            CG (dB)

            12.6

            14.5

            13.9

            10

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq254_HTML.gif (mW)

            5.1

            7.1

            6.8

            5.9

            Margin

            0.9 %

            15.8%

            6.1%

            4.8%

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig11_HTML.jpg
            Figure 11

            Optimization results compared with the nominal optimization trace (projections on the LNA NF-Power space). Red dots correspond to npMOS instances, blue dots to nMOS instances. Robust results do not lie on the Pareto optimal curve.

            5.3. UWB Front-End

            In this subsection, we proceed with optimization, under robustness constraints, of a UWB receiver based on the architecture in [28]. The RF front-end includes two main building blocks, which were both characterized and embedded into a platform library. The first block, shown in Figure 12, consists of the Tx/Rx switch ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq255_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq256_HTML.gif ), the wideband (3.1–4.8 GHz) input matching network ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq257_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq258_HTML.gif , http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq259_HTML.gif , and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq260_HTML.gif ), and the LNA, which features a stagger tuning technique to achieve gain flatness over the wideband of interest. The second block, represented in Figure 13, includes a passive mixer ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq261_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq262_HTML.gif ) and a low-noise buffer amplifier ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq263_HTML.gif ) to boost the mixer gain.
            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig12_HTML.jpg
            Figure 12

            Schematic of the LNA used in the UWB receiver front-end together with its input matching network.

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Fig13_HTML.jpg
            Figure 13

            Schematic of the passive mixer and buffer used in the UWB receiver.

            In the nominal optimization, we aimed at minimizing power consumption ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq264_HTML.gif ) of the RF front-end while meeting system constraints on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq265_HTML.gif , total gain http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq266_HTML.gif , and noise figure ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq267_HTML.gif ). Similar to (14), the robust optimization problem is formulated as follows:

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ15_HTML.gif
            (15)

            where the system performance figures (power, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq268_HTML.gif , gain, and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq269_HTML.gif ) are calculated from the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq270_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq271_HTML.gif using RF cascade equations, as follows:

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_Equ16_HTML.gif
            (16)

            The behavioral model http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq272_HTML.gif is then built out of (16), with some additional validity laws enforcing correct block composition. As in the UMTS optimization problem, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq273_HTML.gif has been used to control the amount of margin on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq274_HTML.gif , hence the architecture margin at optimum. For this particular application, power, http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq275_HTML.gif , and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq276_HTML.gif , the most critical performance parameters, have been given the same relative weight. http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq277_HTML.gif dictates the power consumption margin, while robustness with respect to gain and second-order distortion variations is less of a concern for our UWB communication system. http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq278_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq279_HTML.gif set the system-level margins on noise figure and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq280_HTML.gif of the optimum system design. As in (14), the http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq281_HTML.gif function saturates when margins become too large ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq282_HTML.gif 15%).

            In Table 3, we report the optimal performance as a function of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq283_HTML.gif , together with the main performance figures and their margins. As in the UMTS case, larger values of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq284_HTML.gif imply more aggressive optimizations, better performance, and lower margins. However, this does not necessary translate into lower-power consumption, in this case, since the system-level margin with respect to power has the same weight as the other margins. Since the system performance is more sensitive to http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq285_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq286_HTML.gif , the ellipsoids used to compute http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq287_HTML.gif and http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq288_HTML.gif were selected so that the LNA noise figure and the mixer http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq289_HTML.gif have a weight which is twice the one of the other performance indices. Overall, the final system allows for much wider margins with respect to the nominal solution, albeit at the cost of increased power consumption ( http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq290_HTML.gif 30% for the case http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq291_HTML.gif ).
            Table 3

            UWB RF front-end receiver robust optimization results as a function of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq292_HTML.gif . Larger values of http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq293_HTML.gif decrease the sensitivity on http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq294_HTML.gif in (15).

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq295_HTML.gif

            nom.

            0

            0.1

            0.3

            Gain (dB)

            18.32

            19.84

            17.72

            19.64

            Power (mW)

            7.95

            8.59

            8.33

            10.28

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq296_HTML.gif (dB)

            4.16

            4.16

            3.99

            3.75

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq297_HTML.gif (dBm)

            −24.07

            −24.68

            −21.00

            −18.65

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq298_HTML.gif

             

            0.75

            0.80

            0.46

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq299_HTML.gif

             

            0.84

            1.01

            1.25

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq300_HTML.gif

             

            5.32

            9.00

            11.35

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq301_HTML.gif (dB)

            19.42

            21.57

            20.30

            21.56

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq302_HTML.gif (dB)

            3.81

            4.00

            3.72

            3.56

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq303_HTML.gif (dBm)

            −9.32

            −11.13

            −10.46

            −11.49

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq304_HTML.gif (mW)

            5.8

            6.38

            6.39

            8.44

            Margin

            0.22%

            32.0%

            24.6%

            14.2%

            CG (dB)

            −1.11

            −1.73

            −2.59

            −1.9

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq305_HTML.gif (dB)

            12.79

            11.81

            12.32

            12.07

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq306_HTML.gif (dBm)

            −4.47

            −2.81

            −0.29

            3.83

            http://static-content.springer.com/image/art%3A10.1155%2F2010%2F261583/MediaObjects/13639_2009_Article_216_IEq307_HTML.gif (mW)

            2.15

            2.21

            1.93

            1.84

            Margin

            0.04 %

            17.13%

            0.1%

            0.1%

            As a final comment on the results, we could not perform a Monte Carlo analysis on the actual circuits for any design since the complexity of our systems rules out the possibility of performing any reasonable number of simulations to get meaningful results. In fact, this was an important motivation to introduce robustness early in the design cycle starting from the system level.

            6. Conclusions

            Platform-Based Design (PBD) is a promising methodology for embedded system design, aiming to improve design productivity by encouraging design reuse, orthogonalization of concerns, and system-level optimization. In this paper, we have illustrated the extension of PBD to mixed-signal systems. Furthermore, to ensure robustness with respect to both model and design uncertainties, we have proposed the application, within the PBD framework, of design-centering techniques. The proposed approach allows robust hierarchical design without any assumption on the mathematical properties of the system models, leading to a general formulation that can be used for robust automatic design-space exploration.

            To demonstrate the effectiveness of the proposed design methods in different domains, we presented three case studies: a mixed-signal pipeline ADC and two RF front-ends, respectively, for UMTS and UWB receivers. In all cases, designs were efficiently composed from precharacterized components, as well as optimized at the system level, demonstrating the flexibility of the approach and significant improvements in terms of robustness.

            Authors’ Affiliations

            (1)
            Department of Electrical Engineering and Computer Sciences, University of California at Berkeley
            (2)
            Marvell Chip Design Center, Marvell Semiconductors

            References

            1. Sangiovanni-Vincentelli A: Quo vadis, SLD? Reasoning about the trends and challenges of system level design. Proceedings of the IEEE 2007,95(3):467-506.View Article
            2. Sangiovanni-Vincentelli A: Defining platform-based design. EE-Design 2002.
            3. De Bernardinis F, Nuzzo P, Sangiovanni-Vincentelli A: Robust system level design with analog platforms. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '06), November 2006, San Jose, Calif, USA 334-341.
            4. De Bernardinis F, Nuzzo P, Sangiovanni-Vincentelli A: Mixed signal design space exploration through analog platforms. Proceedings of the 42nd Design Automation Conference (DAC '05), June 2005, Anaheim, Calif, USA 875-880.
            5. Nuzzo P, De Bernardinis F, Sangiovanni-Vincentelli A: Platform-based mixed signal design: optimizing a high-performance pipelined ADC. Analog Integrated Circuits and Signal Processing 2006,49(3):343-358. 10.1007/s10470-006-9067-8View Article
            6. De Bernardinis F: System level mixed signal design with analog platforms, Ph.D. dissertation. University of California, Berkeley, Calif, USA; 2005.
            7. Rabaey JM, De Bernardinis F, Niknejad AM, Nikolić B, Sangiovanni-Vincentelli A: Embedding mixed-signal design in systems-on-chip. Proceedings of the IEEE 2006,94(6):1070-1087.View Article
            8. Liu H, Singhee A, Rutenbar RA, Carley LR: Remembrance of circuits past: macromodeling by data mining in large analog design spaces. Proceedings of the 39th Design Automation Conference (DAC '02), June 2002, New Orleans, La, USA 437-442.
            9. Kiely T, Gielen G: Performance modeling of analog integrated circuits using least-squares support vector machines. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '04), February 2004, Paris, France 1: 448-453.View Article
            10. De Bernardinis F, Jordan MI, Sangiovanni-Vincentelli A: Support vector machines for analog circuit performance representation. Proceedings of the 40th Design Automation Conference (DAC '03), June 2003, Anaheim, Calif, USA 964-969.
            11. Stehr G, Graeb H, Antreich K: Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '04), November 2004, San Jose, Calif, USA 847-854.
            12. Brayton R, Hachtel G, Sangiovanni-Vincentelli A: A survey of optimization techniques for integrated-circuit design. Proceedings of the IEEE 1981,69(10):1334-1362.View Article
            13. Director SW, Hachtel GD: The simplicial approximation approach to design centering. IEEE Transactions on Circuits and Systems 1977,24(7):363-372. 10.1109/TCS.1977.1084353MathSciNetView ArticleMATH
            14. Low KK, Director SW: A new methodology for the design centering of IC fabrication processes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1991,10(7):895-903. 10.1109/43.87599View Article
            15. Ochotta E, Rutenbar R, Carley R: Synthesis of High Performance Circuits. Kluwer Academic Publishers, Dordrecht, The Netherlands; 1996.
            16. Box G, Draper N: Empirical Model-Building and Response Surfaces. John Wiley & Sons, New York, NY, USA; 1987.MATH
            17. Chang H, Charbon E, Choudhury U, et al.: A Top-Down Constraint-Driven Design Methodology for Analog Integrated Circuits. Kluwer Academic Publishers, Dordrecht, The Netherlands; 1997.View Article
            18. Chang H, Liu E, Neff R, et al.: Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters. Proceedings of the Custom Integrated Circuits Conference (CICC '94), May 1994, San Diego, Calif, USA 369-372.View Article
            19. Vassiliou I, Chang H, Demir A, Charbon E, Miliozzi P, Sangiovanni-Vincentelli A: Video driver system designed using a top-down, constraint-driven methodology. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '96), November 1996, San Jose, Calif, USA 463-468.View Article
            20. Van Der Plas G, Gielen G, Sansen W: A Computer-Aided Design and Synthesis Environment. Kluwer Academic Publishers, Dordrecht, The Netherlands; 2004.
            21. Boyd S, Vandenberghe L: Convex Optimization. Cambridge University Press, Cambridge, UK; 2004.View ArticleMATH
            22. Gopalakrishnan P, Xu Y, Pileggi LT: Robust analog/RF circuit design with projection-based posynomial modeling. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '04), November 2004, San Jose, Calif, USA 855-862.
            23. Xu Y, Nausieda I, Hsiung K-L, Boyd S, Li X, Pileggi L: OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. Proceedings of the 42nd Design Automation Conference (DAC '05), June 2005, Anaheim, Calif, USA 632-637.
            24. Wang J, Pileggi LT, Chen T-S, Chiang W: Performance-centering optimization for system-level analog design exploration. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '05), November 2005, San Jose, Calif, USA 421-428.
            25. Press WH, Teukolsky SA, Vetterling WT, Flannery BP: Numerical Recipes in C. 2nd edition. Cambridge University Press, Cambridge, UK; 1992.MATH
            26. Bertsekas DP: Nonlinear Programming. Athena Scientific, Nashua, NH, USA; 1995.MATH
            27. De Bernardinis F, Gambini S, Vincis F, Svelto F, Castello R, Sangiovanni-Vincentelli A: Design space exploration for a UMTS front-end exploiting analog platforms. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '04), November 2004, San Jose, Calif, USA 923-930.
            28. Li Y, Wu C-C, Sangiovanni-Vincentelli A, Rabaey JM: Design and optimization of an MB-OFDM ultra-wideband receiver front-end. Proceedings of the 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC '08), May 2008, Shanghai, China 502-506.
            29. Galton I: Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Transactions on Circuits and Systems 2000,47(3):185-196. 10.1109/82.826744View Article
            30. Murmann B, Boser BE: A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE Journal of Solid-State Circuits 2003,38(12):2040-2050. 10.1109/JSSC.2003.819167View Article

            Copyright

            © Pierluigi Nuzzo et al. 2010

            This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.