Open Access

A Formal Approach to the Verification of Networks on Chip

  • Dominique Borrione1,
  • Amr Helmy1,
  • Laurence Pierre1Email author and
  • Julien Schmaltz2
EURASIP Journal on Embedded Systems20092009:548324

DOI: 10.1155/2009/548324

Received: 1 August 2008

Accepted: 4 February 2009

Published: 22 March 2009

Abstract

The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

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Authors’ Affiliations

(1)
Techniques of Informatics and Microelectronics for Integrated Systems Architecture (TIMA) Laboratory (CNRS, GrenobleINP, UJF)
(2)
Institute for Computing and Information Sciences (ICIS), Radboud University

Copyright

© Dominique Borrione et al. 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.