Open Access

Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

  • Linlin Zhang1, 2, 3Email author,
  • Virginie Fresse1, 2, 3,
  • Mohammed Khalid4,
  • Dominique Houzet5 and
  • Anne-Claire Legrand1, 2, 3
EURASIP Journal on Embedded Systems20092009:542035

DOI: 10.1155/2009/542035

Received: 1 March 2009

Accepted: 17 November 2009

Published: 29 December 2009

Abstract

The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal for dataflow applications with large amount of data. On the opposite, point-to-point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data. For data communication inside the architecture, an efficient time-division multiplexed (TDM) architecture is proposed. This NoC uses a Fat Tree (FT) topology with Virtual Channels (VCs) and flit packet-switching with fixed routes. Two versions of the NoC are presented in this paper. The results of their implementations and their Design Space Exploration (DSE) on Altera Stratix II are analyzed and compared with a point-to-point communication and illustrated with a multispectral image application. Results show that a point-to-point communication scheme is not efficient for large amount of multispectral image data communications. An NoC architecture uses only 10% of the memory blocks required for a point-to-point architecture but seven times more logic elements. This resource allocation is more adapted to image analysis algorithms as memory elements are a critical point in embedded architectures. An FT NoC-based communication scheme for data transfers provides a more appropriate solution for resource allocation.

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Authors’ Affiliations

(1)
Université de Lyon
(2)
CNRS, UMR 5516, Laboratoire Hubert Curien
(3)
Université de Saint-Etienne
(4)
RCIM, Department of Electrical & Computer Engineering, University of Windsor
(5)
GIPSA-Lab

Copyright

© Linlin Zhang et al. 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.