Open Access

Exploiting Process Locality of Reference in RTL Simulation Acceleration

EURASIP Journal on Embedded Systems20072008:369040

DOI: 10.1155/2008/369040

Received: 1 June 2007

Accepted: 4 December 2007

Published: 11 December 2007

Abstract

With the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subset of the simulation processes is executing at any given time, a quality called executive locality of reference. The efficiency of acceleration hardware can be improved when it is used as a process cache. Run-time adaptations are made to ensure that acceleration resources are not wasted on idle processes, and these adaptations may be affected through process migration between software and hardware. An implementation of an embedded, FPGA-based migration system is described, and empirical data are obtained for use in mathematical and algorithmic modeling of more complex acceleration systems.

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Authors’ Affiliations

(1)
Virgina Polytechnic Institute and State University

Copyright

© A. D. Blumer and C. D. Patterson. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.