Table 1 Line of code, area, and time constraints for the validation data.
From: A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis
Algorithm | SS1 | SS2 | SS3 | SS4 | SS5 | SS6 | Ethernet | App 4 |
|---|---|---|---|---|---|---|---|---|
Dev. Time (weeks) | 3.6 | 6.4 | 2.4 | 16.4 | 12 | 17.2 | 16 | 2 |
LOC-VHDL | 994 | 1195 | 776 | 1695 | 760 | 2088 | 3973 | 232 |
Slices | 564 | 2212 | 382 | 888 | 372 | 2171 | 3372 | 750 |
FlipFlops | 913 | 2921 | 1290 | 1366 | 1208 | 2077 | 6149 | 942 |
LUTs | 997 | 3157 | 6453 | 1569 | 6443 | 3458 | 18255 | 567 |
Time Constraint. (ns) | 112 | 128 | 360 | 112 | 360 | 248 | 696 | 56 |