A Shared Memory Module for Asynchronous Arrays of Processors
© Meeuwsen et al. 2007
Received: 1 August 2006
Accepted: 1 March 2007
Published: 9 May 2007
A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μ m CMOS.
- Burks AW, Goldstine HH, von Neumann J: Preliminary discussion of the logical design of an electronic computing instrument. In Collected Works of John von Neumann. Volume 5. Edited by: Taub AH. The Macmillan, New York, NY, USA; 1963:34-79.
- Hennessy JL, Patterson DA: Computer Architecture, A Quantitative Approach. 3rd edition. Morgan Kaufmann, San Francisco, Calif, USA; 2003. chapter Memory Hierarchy Design
- Yu Z, Meeuwsen MJ, Apperson R, et al.: An asynchronous array of simple processors for DSP applications. IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, San Francisco, Calif, USA 428-429.
- Banakar R, Steinke S, Lee B-S, Balakrishnan M, Marwedel P: Scratchpad memory: a design alternative for cache on-chip memory inembedded systems. Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02), May 2002, Estes Park, Colo, USA 73-78.
- Panda PR, Dutt ND, Nicolau A: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems 2000,5(3):682-704. 10.1145/348019.348570View Article
- Patterson D, Anderson T, Cardwell N, et al.: A case for intelligent RAM. IEEE Micro 1997,17(2):34-44. 10.1109/40.592312View Article
- Mai K, Paaske T, Jayasena N, Ho R, Dally WJ, Horowitz MA: Smart memories: a modular reconfigurable architecture. Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada 161-171.
- Baas BM: A parallel programmable energy-efficient architecture for computationally-intensive DSP systems. Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers (ACSSC '03), November 2003, Pacific Grove, Calif, USA 2: 2185-2192.
- Meeuwsen MJ, Sattari O, Baas BM: A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '04), October 2004, Austin, Tex, USA 124-129.
- Chapiro DM: Globally-asynchronous locally-synchronous systems, Ph.D. thesis. Stanford University, Stanford, Calif, USA; 1994.
- Apperson RW: A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains, M.S. thesis. University of California, Davis, Davis, Calif, USA; 2004.
- Mai K, Ho R, Alon E, et al.: Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18- μ m CMOS. IEEE Journal of Solid-State Circuits 2005,40(1):261-275. 10.1109/JSSC.2004.837992View Article
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