Open Access

A SystemC-Based Design Methodology for Digital Signal Processing Systems

  • Christian Haubelt1Email author,
  • Joachim Falk1,
  • Joachim Keinert1,
  • Thomas Schlichter1,
  • Martin Streubühr1,
  • Andreas Deyhle1,
  • Andreas Hadert1 and
  • Jürgen Teich1
EURASIP Journal on Embedded Systems20072007:047580

DOI: 10.1155/2007/47580

Received: 7 July 2006

Accepted: 10 January 2007

Published: 20 March 2007

Abstract

Digital signal processing algorithms are of big importance in many embedded systems. Due to complexity reasons and due to the restrictions imposed on the implementations, new design methodologies are needed. In this paper, we present a SystemC-based solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic system generation for mixed hardware/software solutions mapped onto FPGA-based platforms. Our proposed hardware/software codesign approach is based on a SystemC-based library called SysteMoC that permits the expression of different models of computation well known in the domain of digital signal processing. It combines the advantages of executability and analyzability of many important models of computation that can be expressed in SysteMoC. We will use the example of an MPEG-4 decoder throughout this paper to introduce our novel methodology. Results from a five-dimensional design space exploration and from automatically mapping parts of the MPEG-4 decoder onto a Xilinx FPGA platform will demonstrate the effectiveness of our approach.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64]

Authors’ Affiliations

(1)
Hardware-Software-Co-Design, Department of Copmuter Sciences, Friedrich-Alexander-University of Erlangen-Nuremberg

References

  1. Gries M: Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal 2004,38(2):131-183. 10.1016/S0167-9260(04)00032-XView Article
  2. Haubelt C: Automatic model-based design space exploration for embedded systems—a system level approach, Ph.D. thesis. University of Erlangen-Nuremberg, Erlangen, Germany; 2005.
  3. OSCI : Functional Specification for SystemC 2.0. Open SystemC Initiative, 2002, http://​www.​systemc.​org/​
  4. Grötker T, Liao S, Martin G, Swan S: System Design with SystemC. Kluwer Academic, Norwell, Mass, USA; 2002.
  5. IEEE : IEEE Standard SystemC Language Reference Manual (IEEE Std 1666-2005). 2006.
  6. Lee EA, Sangiovanni-Vincentelli A: A framework for comparing models of computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1998,17(12):1217-1229. 10.1109/43.736561View Article
  7. Falk J, Haubelt C, Teich J: Efficient representation and simulation of model-based designs in SystemC. Proceedings of the International Forum on Specification & Design Languages (FDL '06), September 2006, Darmstadt, Germany 129-134.
  8. http://​www.​mentor.​com/​
  9. http://​www.​forteds.​com/​
  10. Kienhuis B, Deprettere E, Vissers K, van der Wolf P: An approach for quantitative analysis of application-specific dataflow architectures. Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP '97), July 1997, Zurich, Switzerland 338-349.View Article
  11. Kienhuis ACJ: Design space exploration of stream-based dataflow architectures—methods and tools, Ph.D. thesis. Delft University of Technology, Delft, The Netherlands; 1999.
  12. Pimentel AD, Erbas C, Polstra S: A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers 2006,55(2):99-112. 10.1109/TC.2006.16View Article
  13. Pimentel AD, Hertzberger LO, Lieverse P, van der Wolf P, Deprettere EF: Exploring embedded-systems architectures with artemis. Computer 2001,34(11):57-63. 10.1109/2.963445View Article
  14. Mohanty S, Prasanna VK, Neema S, Davis J: Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation. Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems: Software and Compilers for Embedded Systems, June 2002, Berlin, Germany 18-27.
  15. Kianzad V, Bhattacharyya SS: CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems. Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP '04), September 2004, Galveston, Tex, USA 28-40.
  16. Zitzler E, Laumanns M, Thiele L: SPEA2: improving the strength pareto evolutionary algorithm for multiobjective optimization. Evolutionary Methods for Design, Optimization and Control, 2002, Barcelona, Spain 19-26.
  17. Balarin F, Watanabe Y, Hsieh H, Lavagno L, Passerone C, Sangiovanni-Vincentelli A: Metropolis: an integrated electronic system design environment. Computer 2003,36(4):45-52. 10.1109/MC.2003.1193228View Article
  18. Stefanov T, Zissulescu C, Turjan A, Kienhuis B, Deprettere E: System design using Khan process networks: the Compaan/Laura approach. Proceedings of Design, Automation and Test in Europe (DATE '04), February 2004, Paris, France 1: 340-345.View Article
  19. Nikolov H, Stefanov T, Deprettere E: Multi-processor system design with ESPAM. Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), October 2006, Seoul, Korea 211-216.View Article
  20. Kangas T, Kukkala P, Orsila H, et al.: UML-based multiprocessor SoC design framework. ACM Transactions on Embedded Computing Systems 2006,5(2):281-320. 10.1145/1151074.1151077View Article
  21. Eker J, Janneck JW, Lee EA, et al.: Taming heterogeneity - the ptolemy approach. Proceedings of the IEEE 2003,91(1):127-144. 10.1109/JPROC.2002.805829View Article
  22. Cadence : Incisive-SPW. Cadence Design Systems, 2003, http://​www.​cadence.​com/​
  23. Synopsys : System Studio—Data Sheet. 2003.http://​www.​synopsys.​com/​
  24. Buck J, Vaidyanathan R: Heterogeneous modeling and simulation of embedded systems in El Greco. Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES '00), May 2000, San Diego, Calif, USA 142-146.
  25. Herrera F, Sánchez P, Villar E: Modeling of CSP, KPN and SR systems with SystemC. In Languages for System Specification: Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specifications from FDL '03. Kluwer Academic, Norwell, Mass, USA; 2004:133-148.View Article
  26. Patel HD, Shukla SK: Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2005,24(8):1261-1271. 10.1109/TCAD.2005.850819View Article
  27. Patel HD, Shukla SK: Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models. Proceedings of the 14th ACM Great Lakes Symposium on VLSI (GLSVLSI '04), April 2004, Boston, Mass, USA 248-253.View Article
  28. Patel HD, Shukla SK: SystemC Kernel Extensions for Heterogenous System Modeling. Kluwer Academic, Norwell, Mass, USA; 2004.MATH
  29. Liu J, Eker J, Janneck JW, Liu X, Lee EA: Actor-oriented control system design: a responsible framework perspective. IEEE Transactions on Control Systems Technology 2004,12(2):250-262. 10.1109/TCST.2004.824310View Article
  30. Agha G: Abstracting interaction patterns: a programming paradigm for open distribute systems. In Formal Methods for Open Object-based Distributed Systems. Edited by: Najm E, Stefani J-B. Chapman & Hall, London, UK; 1997:135-153.View Article
  31. Lee EA, Messerschmitt DG: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers 1987,36(1):24-35. 10.1109/TC.1987.5009446View Article
  32. Kahn G: The semantics of simple language for parallel programming. Proceedings of IFIP Congress, August 1974, Stockholm, Sweden 471-475.
  33. JTC 1/SC 29; ISO : ISO/IEC 14496: Coding of Audio-Visual Objects. Moving Picture Expert Group
  34. Strehl K, Thiele L, Gries M, Ziegenbein D, Ernst R, Teich J: FunState—an internal design representation for codesign. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2001,9(4):524-544. 10.1109/92.931229View Article
  35. Lee EA, Messerschmitt DG: Synchronous data flow. Proceedings of the IEEE 1987,75(9):1235-1245. 10.1109/PROC.1987.13876View Article
  36. Bilsen G, Engels M, Lauwereins R, Peperstraete J: Cyclo-static dataflow. IEEE Transactions on Signal Processing 1996,44(2):397-408. 10.1109/78.485935View Article
  37. Battacharyya SS, Lee EA, Murthy PK: Software Synthesis from Dataflow Graphs. Kluwer Academic, Norwell, Mass, USA; 1996.View ArticleMATH
  38. Hsu C-J, Ramasubbu S, Ko M-Y, Pino JL, Bhattacharvva SS: Efficient simulation of critical synchronous dataflow graphs. Proceedings of 43rd ACM/IEEE Design Automation Conference (DAC '06), July 2006, San Francisco, Calif, USA 893-898.
  39. Ning Q, Gao GR: A novel framework of register allocation for software pipelining. Conference Record of the 20th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, January 1993, Charleston, SC, USA 29-42.
  40. Parks TM, Pino JL, Lee EA: A comparison of synchronous and cyclo-static dataflow. Proceedings of the 29th Asilomar Conference on Signals, Systems, and Computers, October-November 1995, Pacific Grove, Calif, USA 1: 204-210.View Article
  41. Pareto V: Cours d' Économie Politique. Volume 1. F. Rouge & Cie, Lausanne, Switzerland; 1896.
  42. Blickle T, Teich J, Thiele L: System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems 1998,3(1):23-58. 10.1023/A:1008899229802View Article
  43. IBM : On-Chip Peripheral Bus—Architecture Specifications. 2001.
  44. Zitzler E: Evolutionary algorithms for multiobjective optimization: methods and applications, Ph.D. thesis. Eidgenössische Technische Hochschule Zurich, Zurich, Switzerland; 1999.
  45. Eisenring M, Thiele L, Zitzler E: Conflicting criteria in embedded system design. IEEE Design and Test of Computers 2000,17(2):51-59. 10.1109/54.844334View Article
  46. Deb K: Multi-Objective Optimization Using Evolutionary Algorithms. John Wiley & Sons, New York, NY, USA; 2001.MATH
  47. Schlichter T, Haubelt C, Teich J: Improving EA-based design space exploration by utilizing symbolic feasibility tests. In Proceedings of Genetic and Evolutionary Computation Conference (GECCO '05), June 2005, Washington, DC, USA Edited by: Beyer H-G, O'Reilly U-M. 1945-1952.
  48. Schlichter T, Lukasiewycz M, Haubelt C, Teich J: Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms. Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, March 2006, Klarlsruhe, Germany 309-314.View Article
  49. Haubelt C, Schlichter T, Teich J: Improving automatic design space exploration by integrating symbolic techniques into multi-objective evolutionary algorithms. International Journal of Computational Intelligence Research 2006,2(3):239-254. 10.5019/j.ijcir.2006.65MathSciNetView Article
  50. Streubühr M, Falk J, Haubelt C, Teich J, Dorsch R, Schlipf T: Task-accurate performance modeling in SystemC for real-time multi-processor architectures. Proceedings of Design, Automation and Test in Europe (DATE '06), March 2006, Munich, Germany 1: 480-481.
  51. Buttazzo GC: Hard Real-Time Computing Systems. Kluwer Academic, Norwell, Mass, USA; 2002.
  52. Hastono P, Klaus S, Huss SA: Real-time operating system services for realistic SystemC simulation models of embedded systems. Proceedings of the International Forum on Specification & Design Languages (FDL '04), September 2004, Lille, France 380-391.
  53. Hastrono P, Klaus S, Huss SA: An integrated SystemC framework for real-time scheduling. Assessments on system level. Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS '04), December 2004, Lisbon, Portugal 8-11.
  54. Kempf T, Doerper M, Leupers R, et al.: A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms. Proceedings of Design, Automation and Test in Europe (DATE '05), March 2005, Munich, Germany 2: 876-881.View Article
  55. XILINX : Embedded System Tools Reference Manual—Embedded Development Kit EDK 8.1ia. 2005.
  56. Klaus S, Huss SA, Trautmann T: Automatic generation of scheduled SystemC models of embedded systems from extended task graphs. In System Specification & Design Languages - Best of FDL '02. Edited by: Villar E, Mermet JP. Kluwer Academic, Norwell, Mass, USA; 2003:207-217.
  57. Niemann B, Mayer F, Javier F, Rubio R, Speitel M: Refining a high level SystemC model. In SystemC: Methodologies and Applications. Edited by: Müller W, Rosenstiel W, Ruf J. Kluwer Academic, Norwell, Mass, USA; 2003:65-95.
  58. Hsu C-J, Ko M-Y, Bhattacharyya SS: Software synthesis from the dataflow interchange format. Proceedings of the International Workshop on Software and Compilers for Embedded Systems, September 2005, Dallas, Tex, USA 37-49.
  59. Lieverse P, van der Wolf P, Deprettere E: A trace transformation technique for communication refinement. Proceedings of the 9th International Symposium on Hardware/Software Codesign (CODES '01), April 2001, Copenhagen, Denmark 134-139.
  60. Strehl K: Symbolic methods applied to formal verification and synthesis in embedded systems design, Ph.D. thesis. Swiss Federal Institute of Technology Zurich, Zurich, Switzerland; 2000.
  61. Bukhari KZ, Kuzmanov GK, Vassiliadis S: DCT and IDCT implementations on different FPGA technologies. Proceedings of the 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC '02), November 2002, Veldhoven, The Netherlands 232-235.
  62. Loeffer C, Ligtenberg A, Moschytz GS: Practical fast 1-D DCT algorithms with 11 multiplications. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '89), May 1989, Glasgow, UK 2: 988-991.
  63. Liang J, Tran TD: Fast multiplierless approximation of the DCT with the lifting scheme. Applications of Digital Image Processing XXIII, July 2000, San Diego, Calif, USA, Proceedings of SPIE 4115: 384-395.View Article
  64. Hung AC, Meng TH-Y: A comparison of fast inverse discrete cosine transform algorithms. Multimedia Systems 1994,2(5):204-217. 10.1007/BF01215398View Article

Copyright

© Christian Haubelt et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.